This is a divisional application of application Ser. No. 09/986,299, filed Nov. 8, 2001 now U.S. Pat. No. 7,133,550.
The present invention relates to a method and apparatus for fabricating substrates having circuit patterns, such as semiconductor devices and liquid crystal display devices, and, more particularly, to a technique for inspecting substrate patterns in a fabrication process.
Conventional optical or electron-beam pattern inspection apparatuses have been proposed in JP-A Nos. H5(1993)-258703, H11(1999)-160247, S61(1986)-278706, H7(1995)-5116, H2(1990)-146682, H9(1997)-312318, and H3 (1991)-85742, for example.
FIG. 1 shows an example of an electron-beam pattern inspection apparatus of the type disclosed in JP-A No. H5(1993)-258703. In this conventional electron-beam pattern inspection apparatus, an electron beam 2 emitted from an electron source 1 is deflected in the X direction by a deflector 3, and the electron beam 2 thus deflected impinges on an object substrate 5 under test after passing through an objective lens 4. Simultaneously, while a stage 6 is moved continuously in the Y direction, secondary electrons 7 or the like produced from the object substrate 5 are detected by a detector 8. Thus, a detected analog signal is output from the detector 8. Then, through an A/D converter 9, the detected analog signal is converted into a digital image. In an image processor circuit 10, the digital image thus produced is compared with a reference digital image which is expected to be identical thereto. If any difference is found, the difference is judged to be a pattern defect 11, and the location thereof is determined.
FIG. 2 shows an example of an optical pattern inspection apparatus of the type in JP-A No. H11 (1999)-160247. In this conventional optical inspection apparatus, a light beam emitted from a light source 21 is applied to an object substrate 5 under test through an objective lens 22, and light reflected from the object substrate 5 is detected by an image sensor 23. While a stage 6 is moved at a constant speed, detection of reflected light is repeated to produce a detected image 24. The detected image 24 thus produced is stored into a memory 25. In an image processing circuit 10, the detected image 24 is compared with a previously memorized reference image 27, which is expected to have a pattern identical to that of the detected image 24. If the pattern of the detected image is identical to that of the reference image 27, it is judged that there is no defect, on the object substrate 5. If these patterns are not identical to each other, a pattern defect 11 is recognized, and the location thereof is determined.
As an example, FIG. 3 shows a layout of a wafer 31 corresponding to the object substrate 5. On the wafer 31, there are formed dies 32 which are to be separated eventually as individual identical products. The stage 6 is moved along a scanning line 33 to detect images in a stripe region 34. In a situation where a detection position A 35 is currently taken, a pattern image attained at the detection position A 35 is compared with a pattern image attained at a detection position B 36 (reference pattern image 27), which has been stored in the memory 25. Thus, each pattern image is compared with a reference pattern image which is expected to be identical thereto. In this arrangement, the memory 25 has a storage capacity sufficient for retaining reference pattern image data to be used for comparison, and the circuit structure of the memory 25 is designed to perform a circular-shift memory operation.
In the following two examples, a defect check is conducted using a binary image of an object under test. In synchronization with pattern detection, a judgment is formed on whether a pattern of the object is defective or not while ignoring a possible defect in a particular mask region.
In JP-A No. S61(1986)-278706, there is disclosed an example of a technique for inspecting through-holes on a printed circuit board. In this inspection technique, a printed circuit board having through-holes only in a non-inspection region thereof is prepared beforehand, and an image of the printed circuit board is taken prior to inspection. A binary image indicating the presence/absence of through-holes is thus attained for masking, and it is stored as image data in a masking data storage. At the time of inspection, if a difference found in binary image comparison is located at a position included in a mask region stored in the masking data storage, the difference is ignored for non-inspection.
In JP-A No. H7(1995)-5116, there is disclosed an example of a technique for printed circuit board inspection. In this inspection technique, a pattern is detected to provide binary image data, and using the binary image data, a judgment is formed on whether the detected pattern is normal or not; more specifically, it is checked to determine whether the detected pattern meets any specified regular pattern or not. If not, the detected pattern is judged to be defective.
In the following two examples, using pattern data, a dead zone is provided for the purpose of allowing an error at a pattern boundary in inspection.
In JP-A No. H2(1990)-146682, there is disclosed an example of an inspection technique in which a mask pattern is compared with design data. Through calculation of design data, a pattern is reduced by a predetermined width to attain a reduced image, and also the pattern, is enlarged by a predetermined width to attain an enlarged image. Then, a part common to the reduced image and the enlarged image is extracted to provide a dead zone having a certain width. Thus, using the design data, a mask region is provided so that an error at a pattern boundary having a certain width will be ignored during inspection.
In JP-A No. H9(1997)-312318, there is disclosed an example of a technique for inspecting patterns using a scanning electron microscope (hereinafter referred to just as a “SEM”). Using a reference image acquired in advance, a vicinal area of a pattern edge is set up as a region where no critical defect occurs, since a minuscule deviation of a pattern edge is not regarded as a defect. Thus, an image of the region where no critical defect occurs is ignored. If any difference is found between the reference image and an image of a pattern under test, excluding the region where no critical defect occurs, the difference is judged to be a pattern defect.
In JP-A. No. H3(1991)-85742, there is disclosed an example of a system for carrying out comparative inspection of printed circuit patterns. An image of a candidate defect attained in comparative inspection, is stored in memory. Then, not simultaneously with the comparative inspection, the memorized image is examined to judge whether a difference is actually a defect or not.
On an object under test, there is an area where a considerable difference is found in comparative inspection of patterns, even if the difference is not actually a defect. For example, on an ion-implanted region for formation of a transistor, a non-defective difference may be found in comparative inspection of patterns. Although a difference between a part where ions have been implanted and a part where ions have not been implanted is important at a location of a transistor element, the characteristics of wiring areas, other than transistor element locations, are not affected by the presence/absence of implanted ions. Therefore, in an ion implantation process, rough masking is used to determine where ions are to be implanted. However, in electron-beam inspection of wiring areas, a considerable difference attributable to whether implanted ions are present or not may be detected, resulting in a wrong judgment indicating that the difference represents a defect.
Further, for example, in a power line layer where redundant wiring is provided, even if a part of the wiring is not connected, circuit normality can be ensured by providing a connection at another point. Therefore, in some cases, rough patterning is provided for a power wiring arrangement, so that no-connection on pattern elements are left. In comparative inspection of detected images, a difference attributable to whether a connection is provided or not nay be found, resulting in a wrong judgment indicating that the difference represents a defect.
Still further, for example, on a pattern edge, a detected signal level varies depending on the thickness/inclination of a film thereof. Although up to a certain degree of variation in detected signal output may be ignored, a considerable difference in detected signal output is likely to be taken as a defect mistakenly. A degree of false defect detection is however applicable as an index representing product quality. It is desirable to examine the degree of false defect detection and preclude false defects before carrying out defect inspection.
In the conventional optical/electron-beam pattern inspection apparatuses disclosed in JP-A Nos. H5(1993)-258703 and H11 (1999)-160247, it is not allowed to set up a non-inspection region.
In the inspection techniques disclosed in JP-A Nos. S61 (1986)-278706 and H7 (1995)-5116, there is provided a non-inspection region. However, according to an example presented in JP-A No. S61(1986)-278706, it is required to specify a non-inspection region covering a very large area by using a bit pattern. In application to wafer inspection, a wafer surface area 300 mm in diameter has to be inspected using pixels each having a size of 0.1 μm. This requires an impractically large number of pixels, i.e., seven tera-pixels (seven terabits). According to the inspection technique disclosed in JP-A No. H7 (1995)-5116, any areas other than regular pattern areas are treated as non-inspection regions. Since very complex patterns are formed on a wafer, a non-inspection region cannot be set up just by means of simple pattern regularity.
In the inspection techniques disclosed in JP-A Nos. H2 (1990)-146682 and H9 (1997)-312318, the use of a non-inspection region is limited to a pattern edge, and therefore it is not allowed to set up a non-inspection region at an arbitrary desired location.
In the inspection system disclosed in JP-A No. H3 (1991)-85742, image data of a candidate defect is stored, and then detail inspection is carried out using the stored image data to check whether a difference is actually a defect or not. This approach is applicable to inspection of complex pattern geometries. However, based on predetermined criteria, a judgment is formed on whether a difference is actually a defect or not. Any part may be judged to be normal if requirements based on predetermined criteria are satisfied. That is to say, once a part is judged to be normal, data regarding the part will be lost.
As described above, in the conventional pattern inspection techniques, it is not allowed for a user to set up a non-inspection region effective for a device having a complex, large pattern area to be inspected, such as a wafer. Further, in cases where a considerable difference is found in comparative inspection of detected images even if the difference is not actually a defect, it is likely to be misjudged that the difference represents a defect. In addition to these disadvantages, the conventional pattern inspection techniques are also unsatisfactory as regards stability in detection of minuscule defects.